De-slacking MultiSSE: Improving Timing Analysis and Code Synthesis in ARA, an LLVM-Based Whole-System Compiler for Multi-Core Real-Time Systems

• Typ der Arbeit: Masterarbeit
• Status der Arbeit: abgeschlossen
• Projekte: AHA
• Betreuer: Gerion Entrup, Björn Fiedler, Daniel Lohmann

The MultiSSE analyzes real-time multicore systems to enumerate all possible system states. Without further restriction, this results in a combinatoric explosion, which the MultiSSE tries to mitigate by leveraging BCET and WCET times of individual code parts.

The idea of this thesis is to reduce the amount of states even further by enforcing a longer BCET in the real system and thus making the system more deterministic and predictable. Your task in concrete consists of these subtasks:

• Identify causality chains in the current MSTG (MultiSSE output) to detect graph regions that are caused by a high difference between BCET and WCET. This should happen already during construction thus further minimizing the analysis time.
• Evaluating the graph reduction with the provided examples.
• Developing a mechanism to enforce a longer BCET at the real hardware and evaluating an example system end to end.

Related Publications

RTAS Conference A
MultiSSE: Static Syscall Elision and Specialization for Event-Triggered Multi-Core RTOS

Gerion Entrup, Björn Fiedler, Daniel LohmannProceedings of the 29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'23)2023.
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BibTex Entry

@inproceedings{entrup:23:rtas,
author = {Gerion Entrup and Björn Fiedler and Daniel Lohmann},
booktitle = {Proceedings of the 29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'23)},
entrysubtype = {Conference},
month = {May},
title = {{MultiSSE}: Static Syscall Elision and Specialization for Event-Triggered Multi-Core {RTOS}},
year = {2023},
}

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