MultiSSE: Static Syscall Elision and Specialization for Event-Triggered Multi-Core RTOS

RTAS Conference A
MultiSSE: Static Syscall Elision and Specialization for Event-Triggered Multi-Core RTOS
Gerion Entrup, Björn Fiedler, Daniel LohmannProceedings of the 29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'23)2023.
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Projects: AHA

Abstract

The implementation of static real-time control systems often allows for extensive compile-time optimizations based on RTOS-aware whole-program analyses. Previous work has shown the high optimization potential of control-flow aware static system-call tailoring, but is restricted to single-core systems due to the inherent problem of an exponentially growing analysis state in multicore settings. We present MultiSSE, a multi-core capable and RTOS-aware static whole-system analysis that makes such analyses also feasible on multi-core systems. MultiSSE exploits structural and optional timing information to analyze the core-level control flows as independently as possible from each other, synchronizing their states only when necessary. Thereby, MultiSSE provides means to realize compile-time deadlock detection, lock elision and system-call optimization also on multi-core systems. We evaluate our approach with synthetic benchmarks and a real-world quadrotor application. In all cases, we were able to optimize or even completely elide costly cross-core system calls and system objects.

Source Code

The source code of the ARA framework is available on Github.

Artifacts

We provide a systemd container image with the evaluation artifacts. You will need Systemd-Machined to run the container.

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Slides

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