Analyzing and Optimizing TLB-Induced Thread Migration Costs on Linux/ARM
- Typ der Arbeit: Masterarbeit
- Status der Arbeit: abgeschlossen
- Projekte: AHA
- Betreuer: Björn Fiedler, Christian Dietrich, Daniel Lohmann
- Bearbeiter: Tobias Landsberg
- Ende der Arbeit: 21. Nov 2018
Modern operating systems orchestrate a large number of processes and dispatches their execution onto the available processing elements. However, this hardware multiplexing induces costs and overheads. For example, when a process is migrated to another CPU it looses all its caches. The resulting high cache-miss rate is a handicap to the process and makes CPU-CPU migration expensive.
Another, rather important, cache in modern CPUs is the translation-lookaside buffer (TLB). It saves the result of the translation between virtual adresses and physical addresses, which is performed by the memory-management unit (MMU).
This thesis should investigate if transfering the TLB on inter-core migration is a propper method for reducing thread migration costs. Therefore, TLB migration should be implemented and evaluated on ARM and MIPS based processors.
- Wikipedia EN: Translation Look-aside Buffer
- MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual, Page 553 ff., TLBR, TLBWI
- SP Glossar, "Übersetzungspuffer"