Design and Implementation of a Graphical Simulator for a Pipelined Processor Architecture
The goal of this thesis is to design, implement and evaluate a CPU simulator for a pipelined MIPS-like architecture with a graphical presentation on the block-diagram level. As part of the work you will also explore and characterize different pipeline processor architectures.
The implementation is to be evaluated with a set of test cases for specific units and the whole simulator, covering all edge cases. Other interesting evaluation topics are the simulator's performance characteristics and quantitative and qualitative comparisons with other simulation solutions.
David Patterson, John Hennessy. Computer Organization and Design (987-0123744937)