Implementing AVR Instruction Set Architecture and Evaluating its Resilience using Fault Injection

Fault injection is a common approach to systematically assess the resilience of a system and the effectiveness of software-based counter measures. It tries to mimic either physical causes for single event upsets (by exposing the system to, e.g. heat or radiation) or their effects (by changing logic signals). For the fault injection, we use the simulation-based fault injection framework FAIL*, which extracts program traces and simulates the representative faults.

SAIL is a imperative language for describing the instruction-set architecture (ISA) semantics of processors. Given a Sail definition, the tool can generate executable emulators in C language. So, one can use definitions of different ISAs on the basis of one single tool including type and sanity checking.

First goal is to integrate SAIL (or an executable emulator of an specific AVR ISA generated by SAIL) into the fault injection framework FAIL* we use. The vision is that with SAIL the integration of different or new ISA into FAIL* becomes easier and makes it feasible to evaluate different ISAs due to faults injected.

The next step will be evaluating the AVR architecture comparing other architectures regarding to their resilience against such faults using the simulation-based fault injection framework FAIL*.

  • Will to learn SAIL
  • Experiences in C/C++ and its tooling
  • Interest in implementing an instruction set

Further Reading