Design and Implementation of a Configurable Simulator for an Educational Microcoded Processor Architecture
In this thesis you will design, implement and evaluate a CPU simulator for a microcoded processor architecture that is used in our courses. The simulator should allow the user to modify the processor by adding registers and extending the logic of computational units. As the application is intended for teaching, the user should also be able to interrupt the simulation at cycle-level granularity using breakpoints, and the simulator should support step-by-step execution. The values of registers and the memory should be inspectable at all times. The simulator should include a graphical representation of the CPU at the block-diagram level that dynamically displays the current configuration and helps the user to trace the origin of values and understand the data flow. In addition, you will investigate the feasibility of a rewinding feature that makes it possible for the user to go back in time.
To maximize accessibility and maintainability, the implementation will be based on state-of-the-art web technologies and should run as a standalone application in a web browser. It should reimplement and extend the functionality of a legacy application that is currently used in our courses. Ideally, it will lay the foundation for a unified simulation framework that can be used for different targets in our computer architecture courses.
The implementation is to be evaluated with unit and integration tests to ensure the correct functioning. You will also measure the simulator's performance characteristics to prove its applicability for the designated teaching purposes and undertake quantitative and qualitative comparisons with other simulation solutions.