1. ET-INF
  2. SRA
  3. Theses (BA/MA)
  4. Explicit Hart Control

Explicit Harts: Empowering the OS to Control Hardware Threads

Modern processors contain multiple hardware threads (hart). The CPU switches between them in case one needs to wait before it's next instruction. Otherwise the pipeline would have stalled and wasted computation time. This yields improved utilization of the pipeline and thus increased overall throughput.

Currently the operating system (OS) is not able to control which hart may be executed. In case there are multiple harts one could dedicate one to the operating system and the others to user space applications. The OS may then decide which application might run and vice versa the applications may activate the OS hart if needed. Switching between harts is way faster than software-based context and mode switches which are currently used for system calls.

This thesis should investigate whether explicit control over hart scheduling is profitable in means of improving nonfunctional properties. Therefore a RISC-V processor has to be extended to support this operation and an appropriate operating system has to be invented that uses this facility. The resulting system should be evaluated using simulation techniques as well as synthesizing the processor into an FPGA.

Tl;dr: Introduce hardware thread control instructions to ISA, evaluate costs and benefits

  • C/C++
  • low-level programming
  • hardware construction
  • hardware construction languages (chisel/MyHDL/Verilog)