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Logo: SRA/Leibniz Universität Hannover
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Logo: SRA/Leibniz Universität Hannover
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Speedup Estimation on Heterogenous Hardware

Leitung:apl. Prof. Dr.-Ing. habil. Jürgen Brehm
Bild Speedup Estimation on Heterogenous Hardware

GPU and Multi-Core Programming

Modern computer architectures provide developers with large computational power, they consist of multi-core CPUs and accelerators such as General Purpose GPUs (GPGPUs). The main differences of the computing hardware components are scalability and performance. While multi-core CPUs can only handle a small amount of threads, GPGPUs are designed to handle thousands of threads concurrently. There are three main reasons for engineers to not use the offered computing capabilities efficiently:

Parallelisation is complex

  • The programming environment is different from sequential frameworks.
  • Debugging of parallel programs is highly complex because of the concurrency.

Different parallel programming models

  • Developers have to think and decide about data and task decomposition.
  • The decision about which lines of the code have to be parallelised is not trivial.


  • Parallel code can be mapped on different hardware components like multi-core CPUs or GPGPUs. 
  • The decision about the right mapping depends highly on the characteristics of the software.
  • Code Input Section: The source code is parsed and transformed into an intermediate representation and divided into independent nodes.
  • Speedup Estimation: The available hardware components of the system are determined and subsequently micro benchmarks are performed to evaluate the speed of the considered operations on the different hardware components.
  • Node Predictor: The speedup of single code nodes is predicted based on the micro benchmark results of the speedup estimation module.
  • Post-Processing: Further optimisation through dynamic code analysis is performed.

Within the scope of our survey we focus on providing developers tools with the following characteristics for simplifying the writing of parallel source code:

  • Dividing the source code into independent segments.
  • Estimating the speedup of the single source code parts. Thereby, different hardware architectures like GPGPUs and multi-core CPUs are taken into account.
  • Helping the developers to parallelise source-code parts that provide reasonable speedup.

 Available student theses

Theses can be written in German or English. If you are interested in a topic or have own ideas about a thesis, please do not hesitate to contact us.

Student theses in progress

  • Automatische Parallelisierung von Code-Abschnitten und Vergleich der Ergebnisse unter Berücksichtigung des vorausgesagten Speedups

Supervised student theses

[1] Erstellung eines Modells zur Berechnung des Speedups auf Multi-Core und GPU-Systemen


  • M. Sc. Ioannis Zgeras


Zgeras I., Brehm J., Sprodowski T. (2011): A Model Based Approach for Computing Speedup on Parallel Machines Using Static Code Analysis , PDCS 2011