Program & Presentations

Conference Program

• Monday, Feb. 22, 2010 - Tuesday, Feb. 23, 2010: Tutorials and Workshops
• Wednesday, Feb. 24, 2010 - Thursday Feb. 25, 2010: Conference

Invited Talk: HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors

Karsten Schwan
Ada Gavrilovska
Sudha Yalamanchili

Georgia Institute of Technology

The HyVM project is developing system support for future heterogeneous chip multiprocessors. Such ‘hybrid’ hardware platforms offer opportunities in terms of improved power/performance properties, but pose challenges to systems technologies due to heterogeneous processing cores, non-uniform memory access, and complex software stacks. The HyVM project is creating new hypervisor- and system-level abstractions in support of providing a uniform program execution model for future hybrid computing platforms. Rather than treating accelerators as external devices, the model anticipates future integrated systems by providing sets of virtual processing units for use by both accelerator and commodity programs, offering the resource management support needed to efficiently execute such parallel multi-core applications, and supplying the tool chains needed, at hypervisor level, to permit applications to freely use arbitrary combinations of accelerator and commodity cores. The talk will overview the HyVM project, review results that range from efficient methods for virtualizing accelerators, to online techniques for managing heterogenous system resources, to JIT binary translation for dealing with diverse accelerator targets. The effort is driven by both commercial and high performance applications targeting future hybrid machines.

Invited Talk: Many-Core Computing - Challenges and Opportunities

Dr. Herbert Cornelius
Director Advanced Computing Center Intel EMEA

As we see Moore's Law still continuing for years to come, more and more parallelism is introduced to all computing platforms and at all levels of integration and programming. Computer system designers and programmers can entertain a combination of different hardware and software parallel architectures and programming environments, including homogeneous to heterogeneous architectures and components. With many-core processors on the horizon, there are several challenges but also opportunities on how to implement and program such processors and its related platforms. We will discuss potential many-core architecture technologies and its scalability, usability and programmability. In order to extract the full value and performance of such architectures, we will look at key system components and its potential technologies, i.e. interconnect, cache hierarchy, memory and I/O.

Biography:
Dr. Herbert Cornelius is Director of the Intel Advanced Computing Center in EMEA and manages the Intel Parallel Applications Center worldwide, focusing on scalable parallel algorithms/applications and its implementation based on multi-threading and message-passing utilizing multi-core/multi-processor cluster platforms. Prior to this position he was the EMEA Technical Marketing Manager Enterprise Computing und New Technologies enabling. He joined Intel in 1993 as Computational Scientist in the Scalable Systems Division and has held various technical and management positions in the areas of Applications and Software Engineering. Before joining Intel, he served as Manager Supercomputing Europe at Fujitsu and worked at Cray Research from 1983 to 1990. Prior he worked as Scientific Assistant for Applied Mathematics at the University of Karlsruhe. He received a Ph.D. degree in (Numerical) Mathematics and Diploma degree in Mathematics and Informatics from the Technical University of Berlin, Germany.

Preliminary Timetable:

Preliminary Program

Session 1: Processor Design

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT J. Mische, I. Guliashvili, S. Uhrig, T. Ungerer (Universität Augsburg, Germany)
Complexity-Effective Rename Table Design for Rapid Speculation Recovery Asilioglu, Gorkem; Kaya, Emine Merve; Ergin, Oguz (TOBB University of Economics and Technology, Turkey)
An Embedded GC Module with Support for Multiple Mutators and Weak References Preußer, Thomas B.; Reichel, Peter; Spallek, Rainer G. (TU Dresden, Germany)

Session 2: Embedded Systems

A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems P. Bellasi, W. Fornaciari, D. Siorpaes (Politecnico di Milano, Italy)
Autonomic Workload Management for Multi-Core Processor Systems Zeppenfeld, Johannes; Herkersdorf, Andreas; Bouajila, Abdelmajid; Stechele, Walter (Technische Universität München, Germany)
Firefly flashing synchronization as inspiration for self-synchronization of walking robot gait patterns using a decentralized robot control architecture Jakimovski, Bojan; Meyer, Benjamin; Maehle, Erik (University Lübeck, Germany)

Session 3: Organic Computing and Self-Organization

The JoSchKa System: Organic Job Distribution in Heterogeneous and Unreliable Environments M. Bonn, H. Schmeck (Karlsruhe Institute of Technology – KIT, Germany)
On Deadlocks and Fairness in Self-organizing Resource-Flow systems Steghöfer, Jan-Philipp; Mandrekar, Pratik; Nafz, Florian; Seebach, Hella; Reif, Wolfgang (Universität Augsburg, Germany)
Ad-Hoc- information spread between mobile devices: a case study in analytical modeling of controlled self organization in IT system Kloch, Kamil; Kantelhardt, Jan W.; Lukowicz, Paul; Wuechner, Patrick; de Meer, Hermann (Universität Passau, Germany)

Session 4: Processor design and transactional memory

MLP-aware Instruction Queue Resizing: The Key to Power-Efficient Performance P. Petoumenos, G. Psychou, S. Kaxiras, J.M.C. Gonzalez, J.L. Aragon (University of Patras, Greece University of Murcia, Spain)
Exploiting Inactive Rename Slots for Detecting Soft Errors M. Kayaalp, O. Ergin, O.S. Unsal, M. Valero (1:TOBB University of Economics and Technology, Turkey; 2: Barcelona Supercomputing Center (BSC); 3: Universitat Politecnica de Catalunya (UPC), Spain)
Efficient Transaction Nesting in Hardware Transactional Memory Liu, Yi (Beihang University, China)

Session 5a: Energy management in distributed environments and ad-hoc grids

Decentralized Energy-Management to Control Smart-Home Architectures Becker, Birger; Allerding, Florian; Reiner, Ulrich; Kahl, Mattias; Richter, Urban; Pathmaperuma, Daniel; Schmeck, Hartmut; Leibfried, Thomas (Karlsruhe Institute of Technology – KIT, Germany)
EnergySaving Cluster Roll: Power Saving System for Clusters Dolz, Manuel F.; Fernández, Juan C.; Mayo, Rafael; Quintana-Ortí, Enrique S. (Jaime I University, Spain)
Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids Abdullah, Tariq (1); Bertels, Koen (1); Alima, Luc Onana (2); Nawaz, Zubair (1) (1: Delft University of Technology, Netherlands, The; 2: University of Mons, Belgium)

Session 5b: Performance Modelling and Benchmarking

Compiler-Directed Performance Model Construction for Parallel Programs Schindewolf, Martin (1); Kramer, David (1); Cintra, Marcelo (2) (1: Karlsruhe Institute of Technology – KIT, Germany, 2: University of Edinburgh, UK)
A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures using Fine-Grained Generated Traces Plyaskin, Roman; Herkersdorf, Andreas (Technische Universität München, Germany)
JetBench: An Open Source Real-time Multiprocessor Benchmark Qadri, Muhammad Yasir (1); Matichard, Dorian (2); McDonald Maier, Klaus (1) (1: University of Essex, United Kingdom; 2: Ecole Nationale d’Electronique, Informatique et Radiocommunications de Bordeaux, ENSEIRB, France)

Session 6: Accelerators and GPUs

A tightly coupled accelerator infrastructure for exact arithmetics Nowak, Fabian; Buchty, Rainer (Karlsruhe Institute of Technology – KIT, Germany)
Optimizing Stencil Application on Multi-thread GPU Architecture Using Stream Programming Model Xudong, Fang; Yuhua, Tang; Guibin, Wang; Tao, Tang; Ying, Zhang (National Laboratory for Parallel and Distributed Processing, China)